In a multiple processor environment it is typically the case that some mechanism exists for providing inter-processor communication (IPC). Reference in this regard can be had, as an example, to U.S. Pat. No.: 5,459,836, “Inter-Processor Communication Net”, by Bruce E. Whittaker et al. In this approach each processor in a network of processors is provided with a hardware IPC unit that connects via an IPC signal network to the IPC hardware units of each of the other processors. Each IPC hardware unit provides equal access to the IPC signal network, and also permits multiple signal messages to be received and buffered until serviced by the software of the receiving processor. The software of the receiving processor is made aware of the arrival of a message through an interrupt that is generated by the receiving processor's IPC hardware unit.
Other message passing techniques, in particular interrupt-driven message passing techniques, can be found in commonly-assigned U.S. Pat. No.: 6,105,071, as well as in U.S. Pat. Nos.: 4,633,392, 5,999,969 and 6,321,289.
The use of interrupt-driven message passing techniques is generally preferred over the alternative of polling some status register or flag for an indication that a new message has arrived, especially in real-time, event-driven data processing systems where low latencies are desired.
As may be appreciated, the approach adopted by Whittaker et al. and others exhibits a number of disadvantages. For example, each processor is required to be burdened with carrying the IPC hardware unit, thereby increasing cost, complexity and power consumption. Second, this approach requires the use of a separate signalling bus for implementing the IPC signal network that is connected between the IPC hardware units, thereby further increasing cost and complexity. Third, and related to the first disadvantage, the ability to connect different types of processors from different manufacturers, or even different models of processors from one manufacturer, can become problematic, as each processor must include a compatible IPC hardware unit.
A further layer of non-trivial complexity would be added if it were desired to bidirectionally connect the processors to another hardware unit, e.g., if each processor were to connected to an associated one of a host adapter interface of a common mass storage controller, such as a disk or a tape controller. This is especially true if the messages sent between these processors related to the common shared resource. In this case real-time synchronization issues may exist, making the use of some separate and independent inter-processor signalling bus and IPC units less than desirable.
It is presently known in the art that processors, also known as hosts, can be connected to an associated one of a host adapter interface of a common direct access storage device (DASD), and that a shared DASD dataset can be used for sending a message to the attached hosts from the DASD, in conjunction with polling of the DASD dataset by the attached hosts to discover the existence of the message. However, and as was noted above, the use of polling is not an efficient use of software or the processing power of the host CPU.
Prior to this invention, a satisfactory solution to the problem of sending messages between processors, when the processors are all bidirectionally connected to a common hardware unit, was not known to exist.